Usbtinyisp
USBTinyISP is a project based on a software USB implementation on the Atmel ATTINY2313 by Dick Streefland, [http://dicks.home.xs4all.nl/index.html ]
USB comes in several speeds:
- 4 mbps (low speed)
- 12 mbps (USB 1.1 'full' speed)
- 480 mbps (USB 2.0 high speed)
- 5 gbps (USB 3.0, using 2 new pairs with new SERDES scheme)
The UsbTinyIsp runs on low speed USB, and apparently can get away with a simple resonator instead of a crystal for the clocking. The following USB commands are implemented:
Enumeration:
- Device signals plugin + low speed back to host (device pulls up D- signal with 1k5 pullup to 3V3 (on sample circuit 5V was taken -> different current, but seems to work...).
- Host signals reset (host drives both D+ and D- low -> SE0 bus state, held for few msec means RESET). After this, the D- pullup takes over again.
- Device does Bit decoding on incoming packet (using NRZ encoding on the fly).
- After EOP is detected, packet can be processed
- Device does Bit encoding for the return packet (using NRZ encoding on the fly, a DATA packet or a ACK/NAK packet)
USB Chapter 9 (identification of USB devices in lower software layers)
- SetAddress()
- GetConfiguration()
- GetDescriptor(string)
- SetConfiguration()
The actual functionality is implemented with SETUP packets, followed by an IN packet (back to host) and empty OUT packet that needs to be acked as well. Setup packet fields:
- Request: uint8
- wValue: uint16
- wIndex: uint16
- wLength: uint16
SPI with the UsbTinyIsp
For external SPI transfers, Vendor Request In (0x07) can be used. it accepts no more than 4 bytes, that are put in wValue c1c0,wIndex c3c2). There is no chip-select, and no way of controlling other peripherals on the SPI bus (reset). There are not enough IO buffers on the board to convert the 5V rails of the TINY2313 to the target level (VDDext = 3V3). To work around this, I want to use a simple diode.
First investigation is outputting a clock and bytes, and verify this on the scope. The SPI clock coming out of my tinyISP it looks very distorted - it looks almost like the normal slow clock of ca 10 kHz was interrupted by a 40 kHz clock.
I first need to verify if the binary in the chip is the same as intended.
